How we link two NVIDIA GX10 superchips into a single memory pool to bench models too big for one box — and the exact configuration that finally made it stable.
2
GX10 GB10 superchips, ARM + Blackwell
128GB
unified memory each (~121 GB usable)
200GbE
ConnectX-7 RoCE/RDMA link between them
~240GB
pooled usable memory across the pair
The topology
The config that made it stable
--parallel 1 one KV slot, not four
--flash-attn
q8 KV cache
-fit off skip slow auto-placement
tensor-split 0.30 / 0.70 loan light
64k context
The earlier hangs weren't the cluster — they were config. Four KV slots, f16 cache, a backwards split and the auto-fit step pushed the orchestrator over its 121 GB and froze it. With the settings above, a 124 GB model loads with the orchestrator sitting light at ~40 GB.
The fit ceiling — what the pool can actually hold
Two modes, one slot
One brain at a time. The cluster serves a single slot, so exactly one workload runs against it — gauntlet or gate, never both at once. Live state (GPU, RAM, resident model, tok/s, context, the agent loop) is pushed every 15s to the Fleet page. The second unit is on loan and ships back, so the cluster is a temporary capability — the standing target stays "biggest model that fits one box."
IMR R&D · infrastructure note · the 2×GX10 cluster, June 2026.